1. Field of Invention
The present invention relates to a method of forming a mask pattern for manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a dummy active mask pattern, by which the active regions can be protected from ion implantation.
2. Description of Related Art
Shallow trench isolation (STI), is widely used in manufacturing an integrated circuit. Forming STI includes the steps of forming a trench on the substrate by the anisotropic dry etching and filling the trench with oxide to provide a device insulation area. Therefore, in the process of forming a complementary metal-oxide semiconductor (CMOS) with sub-micron dimensions, STI is a better and scaleable insulation structure, and can prevent a "bird's beak" encroachment in local oxidation. In a conventional method of forming STI, a dummy active pattern is usually formed to prevent a "dishing effect" from occurring on larger STI areas in the process of chemical mechanical polishing (CMP). However, the presence of the dummy active pattern still affects the performance of the semi-conductor devices.
FIGS. 1A to 1C show cross-sectional views of a conventional method in which a dummy active pattern is used to form the STI. As shown in FIG. 1A, after defining a photo-resist layer with a dummy active pattern (not shown in FIG. 1A) on a substrate 100, a plurality of dummy active areas 106 and shallow trenches 108 are formed thereon, and then an insulation layer 110 is deposited on the substrate 100, and the shallow trenches 108 are filled.
Then, as shown in FIG. 1B, the insulation layer 110 is polished by CMP until it is level with the substrate 100, whereby the shallow trenches 108a are formed. Then, a mask pattern (not shown in FIG. 1B) is used in for implanting ions into the substrate 100 to form an N-well 102 and a P-well 104. Then, as shown in FIG. 1C, a dielectric layer 112 is formed on the substrate 100 and a metal layer 114 is sequentially deposited for forming plugs.
In light of the foregoing, although the conventional method of using dummy active areas on the substrate provides a method of preventing the dishing effect while performing CMP on the shallow trench isolation areas, the existence of dummy active areas make the trench isolation so narrow that a parasitic capacitance is formed between metal interconnections and dummy active areas after doping with N-type ions or P-type ions. This is due to the ions being implanted into the dummy active areas. Therefore there is a need to provide a method to prevent parasitic capacitance due to the interaction between dummy active areas and the metal line.